Verilator Nears 4-State Logic, Boosts UVM

This achievement underscores a community-driven effort, with notable contributions from maintainers like Wilson.

This rapid development pace supports ongoing improvements across several key areas, including four-state logic, Universal Verification Methodology (UVM), constrained randomization, SystemVerilog Assertions (SVA), and force release optimizations.

The Verilator project has introduced four-state logic support, addressing the most requested feature from its user base. This advancement allows the simulator to move beyond traditional two-state simulation, enabling more comprehensive verification scenarios.

The implementation utilizes two bits per value—a binary bit and a mask bit—and converts four-state expressions into two-state equivalents. This architectural choice simplifies downstream optimizations, as existing optimization passes do not require extensive modification.

Testing against the I3C core revealed that build times are 3 to 4 times longer compared to standard two-state simulation.

Furthermore, the run time for simulations utilizing four-state logic is approximately 5 times slower. Optimization work remains to be done, although two-state simulation is expected to remain the faster option for performance-critical tasks.

Verilator has reached a significant milestone, with UVM testbenches now generally compiling successfully, though ongoing bug-fixing and scheduling improvements continue. This progress enabled the successful verification of the Coral MPU, an open-source AI accelerator developed by Google.

The Verilator flow was integrated into the Coral MPU's CI/CD pipeline, making simulation possible for a design where it was previously unfeasible.

Historically, the sampling methods employed produced highly skewed distributions, which could impact the thoroughness of verification.

The new implementation focuses on creating a uniform distribution of hits across various solutions. This refinement aims to enhance the quality of generated stimuli.

By generating more uniformly distributed random inputs, Verilator seeks to ensure more comprehensive and reliable testing of hardware designs.